The demand for fast Time To Market (TTM) and Right First Time (RFT) products in the field of semiconductor integrated circuits (ICs) is great in view of the high costs involved in state-of-the-art IC process technologies. A significant barrier to achieving fast TTM and RFT products is the potentially destructive effects of electrostatic discharge in ICs, particularly as technologies become more complex and device geometries decrease. Hence, in any IC design process a circuit strategy to prevent failure due to electrostatic discharge should be implemented.
There are a number of standards organisations, for example JEDEC (Joint Electron Device Engineering Council), Solid State Technology Association, ESDA (Electrostatic Discharge Association) and MIL (United States Military Standards), that define standards for electrostatic discharge testing models which in turn define particular test waveforms and test methodologies. The most widely accepted electrostatic discharge testing model or waveform is that of the “Human Body Model”. IC customers will typically define a required ESD test pass level against a particular model. A typical requirement is for an IC to pass a 2 kV Human Body Model test.
In order to meet these standards, a commonly used approach (e.g. for Mixed Signal RF IC designs) is to provide for each pin-to-pin circuit route (i.e. the route between two pins through the IC) a parallel electrostatic discharge protection route. This is illustrated in FIG. 1 for two input/output (IO) pins of an IC, where the protection route could be for example a pair of back-to-back diodes arranged to breakdown when the pin-to-pin voltage exceeds some predefined voltage (+/−) which is less than the breakdown voltage via the circuit route. It is noted that for each pin-to-pin pair the protection route may not be a direct route. Rather, each pin could be coupled to a different supply voltage rail via its own protection route. The result however would be the same, i.e. breakdown via the protection route when the pin-to-pin voltage exceeds a predefined voltage.
For this electrostatic discharge protection technique to work satisfactorily it is necessary to ensure that the protection routes are sufficiently robust to electrostatic discharge, and that no other electrostatic discharge routes will open prior to the protection routes turning on. However, a combination of ever more complex designs and advanced, high speed technologies with decreasing transistor breakdown voltages, is increasing the likelihood of alternative electrostatic discharge routes within the active circuit, switching on prior to a desired protection route.
If an IC designer can identify potential alternative electrostatic discharge routes in an IC design it may be possible to either re-design the IC or build-in further electrostatic discharge protection to address that particular weakness. This process typically involves a manual inspection of the design, and requires a high level of skill on the part of the designer. The process may be limited to known circuit topologies whose behaviour is well understood.